Patent · US Active

Device with isolation barrier and fault detection

US10992293B2 · kind B2 · utility

1Cited by

2References

24Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Xiong Li · Allen, US
William W. Toth · Garland, US
Honglin Guo · Plano, US
Danyang Zhu · Beijing, CN

Key dates

Filing date	Sep 20, 2018
Grant date	Apr 27, 2021
Priority date	—
Expiry date	Aug 12, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/20
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A device that comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a first clock signal generator. The second semiconductor die comprises a fault detection circuit, the fault detection circuit comprising a second clock signal generator, a first counter coupled to the second clock signal generator, multiple storage devices coupled to the second clock signal generator and to the first counter, a logic gate coupled to the multiple storage devices, a second counter coupled to the logic gate and to the first clock signal generator, and a comparator coupled to the logic gate and the second counter.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.