Synchronized reset for a circuit emulator
US10996723B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2018 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Jan 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.