Memory system, computing system, and methods thereof for cache invalidation with dummy address space
US10997082B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 25, 2019 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Jul 7, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.