Parallel page table entry access when performing address translations
US10997083B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2018 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Sep 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/651
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Address translation circuitry performs virtual-to-physical address translations using a page table hierarchy of page table entries, wherein a translation between a virtual address and a physical address is defined in a last level page table entry of the page table hierarchy. The address translation circuitry is responsive to receipt of the virtual address to perform a translation determination with reference to the page table hierarchy, wherein an intermediate level page table entry of the page table hierarchy stores an intermediate level pointer to the last level page table entry. The translation determination comprises: calculating a higher level pointer to the intermediate level page table entry by applying a first predetermined function to the virtual address, calculating the intermediate level pointer by applying a second predetermined function to the virtual address, and initiating a memory access to retrieve in parallel the intermediate level pointer from the intermediate level page table entry and the translation from the last level page table entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.