Patent · US Active

System and method for computing electrical over-stress of devices associated with an electronic design

US10997332B1 · kind B1 · utility

4Cited by

2References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Taranjit Singh Kukal · Delhi, IN
Siddharth Mohan · San Diego, US
Vikrant Khanna · Noida, IN
Kunal Gupta · Sunnyvale, US
Jasleen Kaur Ahuja · New Delhi, IN
Nikhil Gupta · New Delhi, IN

Key dates

Filing date	Sep 26, 2019
Grant date	May 4, 2021
Priority date	—
Expiry date	Sep 26, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/02
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and splitting, using the at least one processor, the electronic design schematic into a plurality of subcircuits. Embodiments may further include independently simulating each of the plurality of subcircuits to generate simulation results and analyzing the simulation results to determine over-stress associated with the plurality of subcircuits.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.