In-system scan test of chips in an emulation system
US10997343B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2019 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Dec 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318519
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An emulation system may include an emulator. The emulator may include at least one chip and at least one FPGA. The chip may be associated with the FPGA. The FPGA may operate as a coprocessor to implement in-system scan test of the chip. In a scan mode of the in-system scan test, the coprocessor may transmit one or more in-system test instructions to the chip through its existing connections with the chip. The coprocessor may capture test response data from the chip in response to the one or more in-system test instructions through its existing connections with the chip. In an offline mode, the coprocessor may compare the test response data with expected response data to determine if the chips are functioning correctly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.