Data caching circuit, display panel and display device
US10997892B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2020 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Aug 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data caching circuit includes a ring signal counter, a switch, and a first latch. An output terminal of the ring signal counter is connected to a control terminal of the switch. An output terminal of the switch is connected to a control terminal of the first latch. The ring signal counter is configured to input a data transmission starting signal and a clock signal to generate and output a count control signal. A clock signal terminal of the switch is configured to input the clock signal, and the switch is configured to generate and output a data caching control signal according to the input count control signal and clock signal. A data signal input terminal of the first latch is configured to input a data signal. The first latch is configured to latch the data signal according to the data caching control signal input from the control terminal of the first latch. An output terminal of the first latch is configured to output the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.