Signal processor for speech enhancement and recognition by using two output terminals designated for noise reduction
US10997987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2018 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Oct 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG10L2021/02163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A signal processor comprising: an input terminal, configured to receive an input-signal; a voicing-terminal, configured to receive a voicing-signal representative of a voiced speech component of the input-signal; an output terminal; a delay block, configured to receive the input-signal and provide a filter-input-signal as a delayed representation of the input-signal; a filter block, configured to: receive the filter-input-signal; and provide a noise-estimate-signal by filtering the filter-input-signal; a combiner block, configured to: receive a combiner-input-signal representative of the input-signal; receive the noise-estimate-signal; and combine the combiner-input-signal with the noise-estimate-signal to provide an output-signal to the output terminal; and a filter-control-block, configured to: receive the voicing-signal; receive signalling representative of the input-signal; and set filter coefficients of the filter block in accordance with the voicing-signal and the input-signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.