Semiconductor die
US10998305B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2019 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Aug 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A semiconductor die can include: first, second, third, and fourth transistors disposed at intervals, where each two of the first, second, third, and fourth transistors are separated by a separation region to form four separation regions; an isolation structure having a first doping structure of a first doping type, and a second doping structure of a second doping type, to absorb hole carriers and electron carriers flowing between the first, second, third, and fourth transistors; where the first doping structure is located in the separation region to isolate adjacent transistors in the first, second, third, and fourth transistors; and where at least a portion of the second doping structure is surrounded by the first doping structure, and the second doping structure is separated from the first doping structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.