Self-aligned trench MOSFET structures and methods
US10998438B2 · kind B2 · utility
5Cited by
5References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 1, 2019 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Mar 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/146
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOSFET device structure is formed on a semiconductor wafer. The structure includes an array of plurality of MOS gate trenches and self-aligned p+ contact trenches that are formed in a p body region. Trench depth of MOS gate trenches are deeper than the self-aligned p+ contact trenches. P doped shield regions are formed under each MOS gate trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.