Front end circuit for a non-linear sensor comprising a current to voltage converter and a limiting bias circuit respectively connected to the common cathode and the common anode of an array of avalanche photodiode elements
US10998983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2018 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Jul 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/18
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A sensor circuit (10), including a silicon photomultiplier, SiPM, sensor (20), a voltage source (32), a current-to-voltage converter (24), and a limiting bias circuit (34). The SiPM sensor (20) has avalanche photodiode, APD, elements (30) connected in parallel between a cathode (K) and an anode (A). The voltage source (32) is configured to apply a reversed bias voltage (Vb) across the SiPM sensor, so that each APD element operates in reverse-biased Geiger mode, and the APD elements operate in integration mode. The bias circuit (34) is connected between the voltage source (32) and the anode, and is configured to limit currents through the APD elements, and to present an AC load impedance for an alternating current within a predetermined operating frequency range (fo) generated by the APD elements at the anode (A) as well as a DC load impedance, such that said AC load impedance is lower than said DC load impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.