Phase and frequency control for clock-data recovery
US10999049B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2019 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Jul 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock-data recovery circuit includes a variable data path delay, an injection-locked oscillator having a free-running frequency, and circuitry for adjusting at least one of the variable data path delay and the free-running frequency, including a counter configured to count repetitions of a bit value in an input data signal, and further being configured to, on occurrence of a first data pattern in the input data signal, indicative of saturation of inter-symbol interference, measure the input data signal at a first clock edge to determine a first data phase measurement value, measure the input data signal at clock centers immediately preceding and immediately following the first clock edge to determine second and third data phase measurement values, and based on first predetermined relationships among the first, second and third data phase measurement values, adjust the variable data path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.