Reference noise compensation for single-ended signaling
US10999051B2 · kind B2 · utility
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5References
20Claims
0Family size
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Key dates
| Filing date | Jun 18, 2020 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Jun 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0037
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.