Patent · US Active

SerDes systems and differential comparators

US10999055B2 · kind B2 · utility

0Cited by

0References

20Claims

0Family size

Assignee

SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD. · CN

Inventors

Yulin Deng · Tangxia, CN
Xinwen Ma · Shanghai, CN

Key dates

Filing date	Mar 17, 2020
Grant date	May 4, 2021
Priority date	—
Expiry date	Mar 17, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/0337
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A SerDes system is provided. The SerDes system includes channel circuits, a PLL circuit, first and second buffers, and first and second capacitors. Each channel circuit is coupled to the first and second clock lines. The PLL circuit generates a first differential signal including first and second clock signals. The first buffer buffers the first clock signal. The second buffer and buffers the second clock signal. The first capacitor receives the buffered first clock signal and outputs a third clock signal to the first clock line. The second capacitor receives a buffered second clock signal and outputs a fourth clock signal to the second clock line. A swing of a second differential signal comprising the third clock signal and the fourth clock signal is smaller than a swing of the first differential signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.