Localized garbled circuit device
US10999082B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2018 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Jun 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
According to various aspects of the present application, systems and methods are provided for implementing a garbled circuit on a device. Doing so allows the device to perform computations while protecting the computations from being observed or accessed by an adversarial entity. A garbled circuit involves two parties, known as the generator and the evaluator, jointly evaluating a function. Conventionally, a garbled circuit is executed on two different devices in order for the two different parties to jointly calculate the function without each party revealing to the other party private information such as input values to the function. Some embodiments provide for execution of the garbled circuit on a single device by implementing both parties on the device as separate processes. Some embodiments prevent an adversarial entity with physical access to the device from being able to observe calculations performed by the device to evaluate a function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.