Electrical computer system processing architecture for equitable assignment of improvements
US10999217B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2019 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Nov 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06Q40/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An electrical computer system processing architecture for providing fairness amongst client computers of the computer system is disclosed. The electrical computer system processing architecture comprises a plurality of client computers connected to at least one server by a computer network. Each of the client computers is configured to provide requests to the at least one server. The or each server comprises a store for storing requests provided by the plurality of client computers. The or each server is configured to: match complementary requests from the plurality of client computers stored in the store; following matching of complementary requests, assign an indication of how well the requests have been met compared to requests of other client computers of the computer system; accumulate the indications to form an accumulation of indications; and when the accumulation exceeds a predetermined threshold, match future requests in favor of the client computer whose requests have not been met as favorably with requests of other client computers of the computer system, thereby providing fairness amongst client computers of the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.