Analog circuit fault feature extraction method based on parameter random distribution neighbor embedding winner-take-all method
US11002789B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2018 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Sep 6, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An analog circuit fault feature extraction method based on a parameter random distribution neighbor embedding winner-take-all method, comprising the following steps: (1) collecting a time-domain response signal of an analog circuit under test, wherein the input of the analog circuit under test is excited by using a pulse signal, a voltage signal is sampled at an output end, and the collected time-domain response signal is an output voltage signal of the analog circuit; (2) applying a discrete wavelet packet transform for the collected time-domain response signal to acquire each wavelet node signal; (3) calculating energy values and kurtosis values of the acquired wavelet node signals to form an initial fault feature data set of the analog circuit; and (4) analyzing the initial fault feature data by the parameter random distribution neighbor embedding winner-take-all method, to acquire optimum low-dimensional feature data. The invention effectively reduces redundancy and interference elements in the fault features, and greatly improves degree of separation of different fault features and degree of polymerization of samples of same fault category.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.