Systems and methods for managing physical-to- logical address information
US11003373B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2019 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Jan 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for managing physical-to-logical address information in a memory system includes determining whether a memory fragment of a memory block is a last memory fragment of the memory block. The method also includes, in response to a determination that the memory fragment is not the last memory fragment of the memory block: performing a write operation on the memory fragment; storing, in cache associated with the memory system, physical-to-logical address information associated with the memory fragment; and, in response to a determination that the cache is full, writing, to a next memory fragment of the memory block, control metadata associated with physical-to-logical address information stored in the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.