Coalescing adjacent gather/scatter operations
US11003455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2019 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Apr 29, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.