Patent · US Active

System cache optimizations for deep learning compute engines

US11003592B2 · kind B2 · utility

3Cited by

2References

16Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Neta Zmora · Kiryat Yam, IL
Eran Ben-Avi · Haifa, IL

Key dates

Filing date	Apr 24, 2017
Grant date	May 11, 2021
Priority date	—
Expiry date	Apr 24, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06N20/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an example, an apparatus comprises a plurality of compute engines; and logic, at least partially including hardware logic, to detect a cache line conflict in a last-level cache (LLC) communicatively coupled to the plurality of compute engines; and implement context-based eviction policy to determine a cache way in the cache to evict in order to resolve the cache line conflict. Other embodiments are also disclosed and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.