Leakage current reduction in a dual rail device
US11004480B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2019 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Jan 21, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device for reducing leakage current includes a memory cell array, a power switch and a core logic. The memory cell array is electrically connected to a first power rail which supplies a first voltage level. The core logic circuitry is electrically connected to a second power rail via the power switch when the power switch is turned on. The second power rail supplies a second voltage level which is lower than the first voltage level. The power switch is to be turned off by the first voltage level supplied to a gate terminal of the power switch, to thereby disconnect the core logic circuitry in a sleep state from the second power rail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.