Twisted wordline structures
US11004491B2 · kind B2 · utility
0Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2019 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Sep 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to semiconductor structures and, more particularly, to twisted wordline structures and methods of manufacture. The memory array structure includes: a plurality of bitcells comprising memory elements and access transistors; a plurality of bitlines and wordlines which interconnect the bitcells; a plurality of dummy bitcells which intersect with the bitlines and wordlines; and a plurality of twisted wordline strap cells which twist wordlines in the dummy bitcells and connect a higher metal layer in the bitcells to a gate structure of the access transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.