Vertical-type memory device
US11004866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2020 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Feb 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.