Method for manufacturing a resistive memory
US11005041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2017 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Nov 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A method for manufacturing a resistive random access memory includes depositing a layer made of an active material of variable electrical resistance on a substrate containing a first electrode, forming a lower electrode; depositing an electrically conductive layer on the active material layer; etching the electrically conductive layer so as to delimit a second electrode, forming an upper electrode, facing the lower electrode; exposing at least one flank of the upper electrode to an ion beam inclined with respect to the normal to the substrate by an angle (α) comprised between 20° and 65°, so as to implant the ions in a portion of the active material layer adjacent to the flank and located under the upper electrode, the ion implantation conditions being chosen so as to create defects in the structure of the active material and to obtain an average implantation width comprised between 5 nm and 10 nm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.