Duty-cycle correction circuit for DDR devices
US11005468B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2020 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Sep 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for performing duty-cycle correction of an output clock in a Double Data Rate (DDR) system includes: setting a fixed delay of a rising-edge of the output clock as a parameter X which is equal to a digital Master Delay Locked Loop (MDLL) code of the DDR system multiplied by a percentage representing an estimated distortion of the duty-cycle of the output clock from a desired duty-cycle; shifting the rising-edge of the output clock by the fixed delay; and determining whether a duty cycle of the shifted output clock meets the desired duty-cycle. When a duty-cycle of the shifted output clock meets the desired duty-cycle, the fixed rising-edge delay is taken as a final delay code for the output clock; otherwise, a falling-edge of the output clock is shifted by an amount in a range between 0 and NX, wherein N is an integer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.