Phase detector for phase-locked loops
US11005482B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2020 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Jan 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0992
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for phase detection in a phase-locked loop (PLL) control system, such as a millimeter-wave PLL. A PLL control system includes a voltage-controlled oscillator (VCO) circuit and a sub-sampling phase detector (SSPD). The VCO circuit is configured to generate an oscillating VCO output voltage based at least in part on an error signal generated by the SSPD. The error signal is proportional to a phase difference between an oscillating reference input voltage and the oscillating VCO output voltage. The SSPD includes a switched emitter-follower (SEF) sampling network, also referred to in this disclosure as an SEF circuit. In contrast to existing CMOS-based techniques, the SEF sampling network allows the SSPD to operate up to higher frequencies, for example, greater than 100 GHz, than possible using a CMOS sampler, and is also compatible with BiCMOS processes, which generally do not have access to advanced small-geometry CMOS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.