Integrated communication link testing
US11009546B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2019 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Jun 13, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31716
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.