Memory system with multiple striping of raid groups and method for performing the same
US11010076B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 18, 2019 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Jun 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.