Data processing system having a hardware acceleration plane and a software plane
US11010198B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2017 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Aug 4, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system is described herein that includes two or more software-driven host components. The two or more host components collectively provide a software plane. The data processing system also includes two or more hardware acceleration components (such as FPGA devices) that collectively provide a hardware acceleration plane. A common physical network allows the host components to communicate with each other, and which also allows the hardware acceleration components to communicate with each other. Further, the hardware acceleration components in the hardware acceleration plane include functionality that enables them to communicate with each other in a transparent manner without assistance from the software plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.