Fault detection and localization using combinatorial test design techniques while adhering to architectural restrictions
US11010282B2 · kind B2 · utility
1Cited by
55References
18Claims
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Key dates
| Filing date | Jan 24, 2019 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Jun 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3692
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and computer-readable media are described for performing fault detection and localization using Combinatorial Test Design (CTD) techniques and generating a regression bucket of test cases that expose a detected fault in a System Under Test (SUT). The SUT may be a hardware system or a software system. Further, the fault detection and localization may be performed while adhering to architectural restrictions on the SUT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.