Methods and apparatuses for two-qubit gate reduction in quantum circuits
US11010517B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 8, 2019 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Nov 8, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure describes a method, an apparatus, a computer-readable medium, and/or means for reducing two-qubit gates in quantum circuits may include receiving a netlist including information relating to a first plurality of two-qubit quantum gates that form the quantum circuits, performing a controlled gate cancellation operation on the information relating to a first plurality of two-qubit quantum gates to produce a second plurality of two-qubit quantum gates that is functionally equivalent to the first plurality of two-qubit quantum gates, wherein a first number of two-qubit quantum gates in the first plurality of two-qubit quantum gates is larger than a second number of two-qubit quantum gates in the second plurality of two-qubit quantum gates, generating a new netlist containing information about the second plurality of two-qubit quantum gates, and providing the new netlist to implement a functionality of the quantum circuits based on the second plurality of two-qubit quantum gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.