Neural network chip, method of using neural network chip to implement de-convolution operation, electronic device, and computer readable storage medium
US11010661B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2018 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Apr 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A neural network chip and a related product are provided. The neural network chip (103) includes: a memory (102), a data reading/writing circuit, a convolution calculation circuit, wherein the memory is used for storing a feature map; the data reading/writing circuit is used for reading the feature map from the memory and execute an expansion and zero-padding operation on the feature according to configuration information of the feature map, and sending to the convolution calculation circuit (S401); and the convolution calculation circuit is used for performing convolution calculation on the data obtained after the expansion and zero-padding operation to implement a de-convolution operation (S402). The technical solution has advantages of saving memory usage and bandwidth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.