Memory device having an increased sensing margin
US11011228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2020 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Jan 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array including memory cells disposed at points at which word lines and bit lines intersect, a first decoder circuit determining a selected bit line and non-selected bit lines among the bit lines, a second decoder circuit determining a selected word line and non-selected word lines among the word lines, a current compensation circuit providing a current path drawing a compensation current from the selected word line to compensate for off currents flowing in the non-selected bit lines, a first sense amplifier comparing a voltage of the selected word line with a reference voltage and outputting an enable signal, and a second sense amplifier outputting a voltage difference between the voltage of the selected word line and the reference voltage during an operating time determined by the enable signal in a readout operation mode of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.