Patent · US Active

Semiconductor structure and method for the forming same

US11011412B2 · kind B2 · utility

1Cited by
0References
19Claims
0Family size

Assignees

Inventors

Key dates

Filing dateAug 30, 2019
Grant dateMay 18, 2021
Priority date
Expiry dateAug 30, 2039

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/76829
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A semiconductor structure and a method for forming same are provided. In one form, a forming method includes: providing a base, where a core layer is formed on the base, a hard mask layer is formed on the core layer, and a first mask opening is formed in the hard mask layer; forming a first mask trench in the core layer exposed from the first mask opening, the first mask trench including a plurality of mask sub-trenches along an extending direction, where the mask sub-trenches are isolated from each other using the core layer exposed from the first mask opening; forming a first spacer on a side wall of the mask sub-trench; removing a core layer of a region in which the first mask opening is located, and forming, at a position corresponding to the core layer, a second mask trench enclosed by the first spacer and the base, the second mask trench and the first mask trench being isolated from each other using the first spacer; and forming a second spacer on a side wall of the second mask trench, where both the first spacer and the base, and the second spacer and the base, enclose a first target trench. The first spacer and the second spacer whose side walls contact with each other are …

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.