High-reliability electronic packaging structure, circuit board, and device
US11011477B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2017 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Mar 30, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high-reliability electronic packaging structure includes a plurality of packaging layers and mechanical support layers. An electrically functional solder joint is provided in a first area of each of the packaging layers, and any two adjacent packaging layers are coupled using electrically functional solder joints. A mechanical support layer is disposed in a second area of each of the packaging layers, and the mechanical support layer is configured to support the two adjacent packaging layers. The first area is provided on a periphery of the second area. Hence, a problem that an internal silicon chip at an upper packaging layer or a lower packaging layer fractures and fails when the upper packaging layer or the lower packaging layer is subject to a mechanical load can be resolved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.