Vertical memory device
US11011536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2018 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Mar 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/292
Abstract
A vertical memory device includes gate electrodes spaced apart from each other in a first direction. Each of the gate electrodes extends in a second direction. Insulation patterns extend in the second direction between adjacent gate electrodes. A channel structure extends in the first direction. The channel structure extends through at least a portion of the gate electrode structure and at least a portion of the insulation pattern structure. The gate electrode structure includes at least one first gate electrode and a plurality of second gate electrodes sequentially stacked in the first direction on the substrate. Lower and upper surfaces of a first insulation pattern are bent away from the upper surface of the substrate along the first direction. A sidewall connecting the lower and upper surfaces of the first insulation pattern is slanted with respect to the upper surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.