Multi-level loop cut process for a three-dimensional memory device using pitch-doubled metal lines
US11011581B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2019 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Jun 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
Abstract
First elongated loop-shaped conductive material portions are formed over a substrate. A two-dimensional array of memory pillar structures is formed over the first elongated loop-shaped conductive material portions. Second elongated loop-shaped conductive material portions over the two-dimensional array of memory pillar structures. Each of the elongated loop-shaped conductive material potions includes a respective pair of line segments and a respective pair of end segments adjoined to ends of the respective pair of line segments. A moat trench that at least partially laterally encloses the two-dimensional array of memory pillar structures can be formed by performing an anisotropic etch process that removes parts of the first and second elongated loop-shaped conductive material portions, thereby separating each loop-shaped conductive material portion into two disjoined line segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.