Patent · US Active

Semiconductor storage device

US11011699B2 · kind B2 · utility

0Cited by
4References
10Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 3, 2020
Grant dateMay 18, 2021
Priority date
Expiry dateMar 3, 2040

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10N70/8828
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A semiconductor storage device includes first to third wirings extending in a first direction and adjacent in a second direction intersecting the first direction, fourth to sixth wirings extending in the second direction and adjacent in the first direction, memory cells each having one end connected to one of the first to third wirings and the other end connected to one of the fourth to sixth wirings, a circuit configured to output a first voltage, second and third voltages higher than the first voltage, a fourth voltage higher than the second voltage and the third voltage, and a fifth voltage higher than the fourth voltage. In a write operation for memory cells connected to the first and fourth wirings, the first, fourth, second, fifth and third voltages are transferred to the first, second, third, fourth, and fifth wirings, respectively, and the third voltage is transferred to the sixth wiring.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.