Demultiplexer and method of controlling the same, and display device
US11012274B2 · kind B2 · utility
1Cited by
0References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2019 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Oct 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D1/2209
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A demultiplexer includes a voltage boost circuit and at least one data selection output circuit. The voltage boost circuit is coupled to N second-stage selection signal input terminals and N first-stage selection signal input terminals, N is greater than or equal to 2, and N is a positive integer. Each data selection output circuit is coupled to a data input terminal, N data output terminals and the N first-stage selection signal input terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.