Clock control circuit and clock control method
US11016525B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Oct 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock control circuit includes a clock source, a reset signal source, a register group with a plurality of first registers, and a clock control unit including a clock adjusting module and a clock gating. wherein a first receiving end of the clock adjusting module is connected to the clock source, a second receiving end of the clock adjusting module is connected to the reset signal source; a first receiving end of the clock gating is connected to an output end of the clock adjusting module, a second receiving end of the clock gating is connected to the clock source, an output end of the clock gating is connected to one end of the register group, and the other end of the register bank is connected to the reset signal source. Reset of the register group in the circuit is not limited by one clock period to avoid circuit function errors and power consumption, and have high applicability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.