Single chip system and reset method for single chip system
US11016548B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2017 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Feb 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single chip system is disclosed, which includes: a reset pin (110), a control unit (120), a central processing unit CPU (130) and a peripheral (140), the single chip system (100) is connected to a master control system (200) via an end of the reset pin (110), the other end of the reset pin (110) is connected to the control unit (120), and the control unit (120) is connected to the CPU (130) and the peripheral (140), where the master control system (200) controls the reset pin (110) to output a reset electrical level; and the control unit (120) detects a signal duration of the reset electrical level output by the reset pin (110), and trigger to wake or reset a single chip according to the signal duration of the reset electrical level, a signal duration for triggering wakeup is different from a signal duration for triggering a reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.