Processor and instruction operation method
US11016771B2 · kind B2 · utility
0Cited by
0References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | May 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed in embodiments of the present disclosure are a processor and an instruction operation method. The method includes obtaining criticality information of an instruction, wherein the criticality information of the instruction indicates importance degree of the instructions in a running process of a program; determining an operation sequence of the instruction based on the criticality information; and performing operations for the instruction based on the determined operation sequence of the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.