System and method for improved handling of memory failures
US11016835B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Nov 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F18/214
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information handling system includes a dual in-line memory module (DIMM) coupled to a memory controller. The memory controller provides interrupts to a processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor that receives the interrupts, accumulates a count of the interrupts, and provides an error indication when the count exceeds an error threshold. In accumulating the count, the failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when a training coefficient for the DIMM is greater than a deviation threshold, and has a second value when the training coefficient for the DIMM is less than the deviation threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.