Storage device or memory controller with first direct memory access engine configured to control writing first data into buffer memory and second direct memory access engine configured to control transmitting written first data to external host device
US11016912B2 · kind B2 · utility
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12References
20Claims
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Assignee
Inventor
Key dates
| Filing date | Oct 21, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Oct 21, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller according to example embodiments of the inventive concept includes a system bus, a first direct memory access (DMA) engine configured to write data in a buffer memory through the system bus, a snooper configured to output notification information indicating whether the data is stored in the buffer memory by snooping around the system bus, and a second direct memory access (DMA) engine configured to transmit the data written in the buffer memory to a host in response to the notification information from the snooper.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.