Digital processing connectivity
US11016930B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 17, 2018 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | May 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17387
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A connectivity has a first network (25) of signal-links interconnecting a large plurality of address-bearing, computing cells (20 and 22). Some of the links are selectable according to addresses hierarchically ordered along a recursive curve. Most of the address-designated links that form the network are switchably operable between cells such that a first selectable set of cells along one segment of the recursive curve form signal-routes to a second selectable set of cells, along a second segment. For receipt of instructions and for synchronisation, some segments have a switchable signal-path from one controlling cell of that segment. A second network (23) has signal-links interconnecting a plurality of processing cells (19 and 21) some of which control the loading of data into cells of the first network. The computing and processing cells have pairwise matching of addresses and are pairwise coterminous, which ensures that control of the connectivity by second network (23) is directed to localisably-selectable segments of first network (25).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.