Cross point resistive memory device with compensation for leakage current in read operation
US11017853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Nov 21, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and an operating method of the memory device, the memory device including a memory cell array including a plurality of memory cells respectively arranged at points at which a plurality of word lines and a plurality of bit lines cross; and a control logic circuit configured to precharge a selected word line connected to a selected memory cell and precharge a selected bit line connected to the selected memory cell in a read operation, wherein the control logic circuit is further configured to precharge a first unselected word line among unselected word lines to a second voltage when the selected word line is precharged to a first voltage, a level of the first voltage is lower than a level of a third voltage applied to an unselected bit line when the selected word line is precharged to the first voltage, and a level of the second voltage is higher than the level of the third voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.