Multi-chip package
US11017877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Aug 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/386
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.