Power semiconductor device with reliably verifiable p-contact and method

US11018051B2 · kind B2 · utility

Assignee

• Infineon Technologies Dresden GmbH & Co. KG · DE

Inventors

• Markus Beninger-Bina · Großhelfendorf, DE
• Matteo Dainese · Munich, DE
• Ingo Dirnstorfer · Eindhoven, NL
• Erich Griebl · Dorfen, DE
• Johannes Georg Laven · Taufkirchen, DE
• Anton Mauder · Kolbermoor, DE
• Hans-Joachim Schulze · Taufkirchen, DE

Key dates

• Filing date: Aug 20, 2019
• Grant date: May 25, 2021
• Expiry date: Aug 20, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/117
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method includes: forming trenches extending from a surface along a vertical direction into a semiconductor body, facing trench sidewalls of two adjacent trenches laterally confining a mesa region of the semiconductor body along a first lateral direction; forming a body region in the mesa region, a surface of the body region in the mesa region at least partially forming the semiconductor body surface; forming a first insulation layer on the semiconductor body surface; subjecting the semiconductor body region to a tilted source implantation using at least one contact hole in the first insulation layer at least partially as a mask for forming a semiconductor source region in the mesa region. The tilted source implantation is tilted from the vertical direction by an angle of at least 10°. The semiconductor source region extends for no more than 80% of a width of the mesa region along the first lateral direction.