Power semiconductor module with low gate path inductance
US11018109B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 17, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Jun 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power semiconductor module, including a housing; a power semiconductor chip within the housing; power terminals protruding from the housing and electrically interconnected with power electrodes of the semiconductor chip; and auxiliary terminals protruding from the housing and electrically interconnected with a gate electrode and one of the power electrodes; wherein three auxiliary terminals are arranged in a coaxial auxiliary terminal arrangement, which comprises an inner and two outer auxiliary terminals, which are arranged on opposing sides of the inner auxiliary terminal. The inner auxiliary terminal is electrically interconnected with the gate electrode or one of the power electrodes and the two outer auxiliary terminals are electrically connected with the other one of the gate electrode and the one of the power electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.