Antifuse OTP structures with hybrid low-voltage devices
US11018143B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2020 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Mar 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/603
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An antifuse One-Time-Programmable memory cell includes a substrate, and a hybrid select transistor and a hybrid antifuse capacitor formed on the substrate. The hybrid select transistor includes a first gate dielectric layer formed on the substrate, wherein the first gate dielectric layer is thinner than 40 nm, a first high-voltage junction formed in the substrate, and a low-voltage junction formed in the substrate. The hybrid antifuse capacitor includes a second gate dielectric layer, wherein the second gate dielectric layer is thinner than 40 nm, which enables a low-voltage antifuse capacitor device, a second gate formed on the gate dielectric layer, a second high-voltage junction formed in the substrate, and a third high-voltage junction formed in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.